BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//132.216.98.100//NONSGML kigkonsult.se iCalcreator 2.20.4//
BEGIN:VEVENT
UID:20260525T160228EDT-5630F171zu@132.216.98.100
DTSTAMP:20260525T200228Z
DESCRIPTION: \n\nAbstract\n\nThis thesis introduces a many-stage CMOS Opera
 tional Transconductance Amplifiers (OTAs) design technique that allows cas
 cading identical gain stages (for arbitrarily scalable ultra-high DC gain)
  while driving an ultra-wide range of capacitive loads (CLs). At the heart
  of the proposed design technique\, is a new generalized theory on the rel
 ationship between frequency response and settling time of CMOS OTAs in the
  presence of Pole-Zero (P-Z) pairs (or doublets). Interestingly\, the pres
 ence of P-Z pairs/doublets in the open-loop frequency response of CMOS OTA
 s has always been considered detrimental to the closed-loop operation of C
 MOS OTAs. However\, the new proposed theory is showing how to reduce the i
 mpact of such P-Z pairs on the closed-loop operation of CMOS OTAs - using 
 low-frequency zeros and cascaded-gain stages – consequently revealing unta
 pped opportunities for many-stage CMOS OTA design. The proposed scalable d
 esign of the many-stage CMOS OTA ensures stability\, when configured in cl
 osed loop\, by means of a new frequency compensation technique that relies
  on low-frequency left-half-plane zeros to allow the proposed OTA to opera
 te for a desired closed-loop behavior. The proposed design realizes a CMOS
  OTA with scalable-gain that increases in 25 dB increments per stage\, ach
 ieving a total gain from 50 dB to 200 dB for a 2-stage to an 8-stage confi
 guration\, respectively. The design is verified through extensive simulati
 ons based on a standard TSMC 65 nm CMOS process. Also\, as a proof-of-conc
 ept\, the design has been validated by fabricating 2-\, 3-\, and 4-stage C
 MOS OTAs\, and the measurement results show that the 2-stage OTA is achiev
 ing a DC gain of 50 dB with a CL-drivability ratio of 10\,000x\, the 3- st
 age OTA is achieving a DC gain of 70 dB with a CL-drivability of 1\,000\,0
 00x\, and the 4-stage OTA is achieving a DC gain of 90 dB with a CL-drivab
 ility of 1\,000\,000x. This is a 10-to-1000- time improvement in the state
 -of-the-art.\n
DTSTART:20220721T140000Z
DTEND:20220721T160000Z
LOCATION:Room 603\, McConnell Engineering Building\, CA\, QC\, Montreal\, H
 3A 0E9\, 3480 rue University
SUMMARY:PhD defence of Mahmood Mohammed - On route to infinite gain CMOS Op
 erational Transconductance Amplifiers and its impact on speed and capaciti
 ve load drivability of closed-loop analog applications
URL:/ece/channels/event/phd-defence-mahmood-mohammed-r
 oute-infinite-gain-cmos-operational-transconductance-amplifiers-and-340385
END:VEVENT
END:VCALENDAR